The presently disclosed and claimed inventive concept(s) relates to compositions and methods for selectively removing hard mask and other residues from integrated circuit (IC) device substrates, and, more particularly, to compositions and methods useful for selectively removing TiN, TaN, TiNxOy, TiW, Ti and W hard mask, and hard masks comprising alloys of the foregoing, as well as other residues from such substrates comprising low-k dielectric materials, TEOS, copper, cobalt and other low-k dielectric materials, using a carboxylate compound.
Plasma dry etching is commonly used to fabricate vertical sidewall trenches and anisotropic interconnecting vias in copper (Cu)/low-k dual damascene fabrication processes. As the technology nodes advance to 45 nm and smaller, the decreasing size of the semiconductor devices makes achieving critical profile control of vias and trenches more challenging. Integrated circuit device companies are investigating the use of a variety of hard masks to improve etch selectivity to low-k materials and thereby gain better profile control.
In order to obtain high yield and low resistance, polymer residues on the sidewalls and the particulate/polymer residues at the via bottoms that are generated during etching must be removed prior to the next process step. It would be very beneficial if the removal composition (cleaning solution) can also effectively etch the hard mask to form an intermediate morphology, e.g., a pulled-back/rounded morphology, or completely remove the hard mask. A pulled-back/rounded morphology could prevent undercutting the hard mask, which, in turn, could enable reliable deposition of barrier metal, Cu seed layer and Cu filling. Alternatively, fully removing the hard mask using the same composition could offer numerous benefits to downstream process steps, particularly chemical mechanical polishing (CMP), by eliminating a need for barrier CMP.
Following almost every step in the fabrication process, e.g., a planarization step, a photolithography step, or an etching step, removal (cleaning) processes are required to remove residues of the plasma etch, photoresist, oxidizer, abrasive, metal and/or other liquids or particles that remain and which can contaminate the surface of the device if they are not effectively removed. Fabrication of advanced generation devices that require copper conductors and low-k dielectric materials (typically carbon-doped silicon oxide (SiOCH), or porous low-k materials) give rise to the problem that both materials can react with and be damaged by various classes of prior art cleaners.
Low-k dielectrics, in particular, may be damaged in the removal process as evidenced by etching, changes in porosity/size, and ultimately changes in dielectric properties. Time required to remove residues depends on the nature of the residue, the process (heating, crosslinking, etching, baking, and/or ashing) by which it was created, and whether batch or single wafer removal processes can be used. Some residues may be cleaned in a very short period of time, while some residues require much longer removal procedures. Compatibility with both the low-k dielectric and with the copper conductor over the duration of contact with the removal composition is a desired characteristic.
During back-end-of-line (BEOL) IC fabrication processes, i.e., dual damascene processes, TiN, TaN, TiNxOy, TiW, Ti, and/or W (including alloys of Ti and W) are used as an hard mask in the formation of vias and trenches to gain high selectivity to low-k dielectric materials during dry etching steps. Effective removal compositions are required that can selectively remove the TiN, TaN, TiNxOy, TiW, Ti or W, be compatible with low-k materials, copper, cobalt and other dielectric materials, and also simultaneously remove unwanted etching residues and Cu oxide from the resulting dual damascene structure. Beyond selective removal, it is also highly desirable that the achievable removal rate of a hard mask (A/min) for the removal composition be maintained substantially constant for an extended period of time.
With the continuing reduction in device critical dimensions and corresponding requirements for high production efficiency and reliable device performance, there is a need for such improved removal compositions.